Conventional amplifiers configured to have current flowing into a common source of a pair of similar devices are well known in the art. The arrangement is commonly referred to as a “long-tailed pair”, where the input signal is applied differentially between the gates of the pair of devices. A second stage of such an amplifier is derived from a load network of some kind, and can be a commonly used mirror arrangement of MOS devices. These may be NMOS devices, PMOS devices, a pair of JFET devices, bipolar devices, GasFETS, or any other three-terminal active device.
The current into the long tailed pair of devices is derived from a device configured as a current source that delivers constant current. One load network that is well known is commonly called a “current mirror” arrangement or a “folded cascode” arrangement. For example, a long tailed pair may be implemented with NMOS FET devices, where the common connection is the source of each device. The input is the voltage between the gates of the devices, and the output is the relative current levels in the drains of the devices. In most all uses of a long tailed pair, the circuit operates on a continuous input current, the “tail current”. This current is a nominally fixed parameter and is split into the outputs of the long-tailed pair as controlled by the relative input voltages.
For example, in two devices arranged as along tailed pair, a current of 1 mA may be sunk from the common source connection. The gate voltage of the left hand device may be configured to be 10 mV higher than the gate voltage of the right hand device. As a result, the current flow in the left hand device drain will be higher than the current flow in the right hand device. For example, the left hand device may have a 600 μA drain current and the right hand device may have 400 μA drain current. Thus, the gate voltage difference has been converted into a drain current difference. The drain current difference is then passed to the load network, such as a mirror or folded cascode, and the current difference is processed to generate the signal to succeeding stages of the circuit.
In conventional circuits, the signal input representation is the voltage difference, and the signal output representation is the current difference. The load network operates to convert the current difference back to a voltage difference upon in which the next stage may operate. Therefore, the load network's primary characteristic is its impedance, the load network's transfer characteristic from current to voltage. This current to voltage conversion is necessitated by succeeding stages of the device, where the devices are voltage input devices, and may include other long tailed pairs. All cascode or folded cascode arrangements simply defer this ultimate and necessary step of current to voltage conversion. Consequently, in implementing a circuit with a long-tailed pair, a designer is concerned with the output impedance, since this will limit the maximum achievable resistance in the current to voltage conversion process, resulting in lower gain.
Consider further the means to generate the current input to the long-tailed pair. In the example above, this may be derived from a device configured as a current source, typically an NMOS FET with its source at ground and gate at a fixed bias voltage. This will generate a current in the drain that is roughly a constant current. This and other current source configurations have a limited output voltage over which the current is roughly constant. The output terminal has an output compliance voltage that limits the range of operating voltages of the long tailed pair. In one example, for NMOS devices, the input common mode range is limited at the low side by the saturation of the current source.
Switched capacitor circuits are also well known, where a charge is manipulated between capacitors to represent the signal being processed. Signal processing functions are implemented by possibly sharing charge with different sized capacitors or by inspecting the voltage present on a capacitor, thus related to its charge by Q=VC, and forcing this voltage to appear across a differently sized capacitor, thus re-creating a charge Qout=Qin*Cout/Cin. The element that connects the capacitors one to the other to enable charge flow is a switch. The resulting equilibrium condition that signals the end of the charge transfer process is the absence of any voltage across the switch. It is this final equilibrium condition, where there is no voltage across the switch that constrains all switched capacitor operations to be of the two types, charge sharing or intermediate voltage replication. As a result, after the charge transfer process is complete, no voltage exists across the switch.
Therefore, there exists a need for an amplifier circuit with less attenuation and higher gain, and with increased input common mode range. As will be seen below, the invention addresses these needs in an elegant manner.